(a) Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device in which propagation of noise between two circuit blocks can be reduced.
(b) Description of Related Art
Semiconductor device comprising so-called "twin-wells" have been developed for realizing microminiaturization of semiconductor devices such as MOS-FETs. In such twin-well semiconductor devices, the semiconductor substrate is made of a semiconductor material of a first conductive type, and a first well of the first conductive type and a second well of a second conductive type opposite to the first conductive type are formed in pair in the vicinity of a main surface of the semiconductor substrate. Transistors are formed on and within the pair of wells to form desired circuits. Twin-well semiconductor devices are used, for example, for hybrid circuits including an analog circuit and a digital circuit in combination. In such hybrid circuits, it is important to reduce noise propagating from the digital circuit to the analog circuit.
FIG. 1A is a schematic plan view of a conventional twin-well semiconductor device for an analog/digital hybrid circuit, and FIG. 1B is a sectional view taken along dashed line B-B' of FIG. 1A. In the vicinity of a main surface of a P-type semiconductor substrate (P-substrate) 30 having a first impurity concentration, a P-well 33 and two N-wells 32 each having an impurity concentration higher than the first impurity concentration are formed on an undoped region 31 of the P-substrate 30. Each of N-wells 32 is located adjacent to the P-well 33 in twin well fashion. Further, there are formed circuit blocks CB31 and CB32 each having a circuit area spreading over both one of the N-wells 32 and the P-well 33. For example, circuit block CB31 is an analog circuit block, while circuit block CB32 is a digital circuit block which constitutes a noise source against the analog circuit block CB31.
A P+ diffused layer 34 is formed in the P-well 33 to shield circuit block CB31 against circuit block CB32, and is electrically connected to a ground line 36 through contact holes 35 formed in an insulator layer 37. With this arrangement, the electric potential at a portion of the P-well 33 located at the periphery of circuit block CB31 is stabilized so that the amount of noise propagating from circuit block CB32 to circuit block CB31 is reduced.
In the conventional semiconductor device shown in FIGS. 1A and 1B, the undoped region 31 of the P-substrate 30 having a first impurity concentration, including an impurity at NA=1E15 cm-3 (10.sup.15 atoms/cm.sup.3) for example, and the P-well 33 having a second impurity concentration, including an impurity at NA=1E17 cm-3 for example, are both disposed between circuit block CB32 and circuit block CB31. Therefore, as illustrated in FIG. 1B, circuit block CB32 and circuit block CB31 are coupled with each other through an equivalent resistance R31 of the P-well 33 formed in the vicinity of the main surface of the P-substrate 31 and an equivalent resistance R32 of the undoped region 31 of the P-substrate 30 located below the P-well 33.
For example, the resistivity r.sub.PSUB of the undoped region 31 of the P-substrate 30 is about 12 .OMEGA.-cm whereas the resistivity r.sub.PWEL of the P-well 33 is about 0.3 .OMEGA.-cm. Accordingly, it can be said that the P-well 33 has a considerably low resistivity (i.e., about 1/40) as compared to the undoped region 31 of the P-substrate 30. Since the equivalent resistances R31 and R32 are proportional to the resistivities of the P-well 33 and the undoped region 31 of the P-substrate 30, respectively, the relationship between the equivalent resistances R31 and R32 becomes R31&lt;&lt;R32, taking account of their spreading resistances, even though the depth of the P-well 33 is smaller than the depth of the undoped region 31.
Since the ground line 36 and the P+ diffused layer 34 are not ideal conductors and have some impedances, noise propagating through the P-well 33 having a small resistance, i.e., through the equivalent resistance R31, cannot be sufficiently reduced, even while noise propagating through the P-substrate 31, i.e., through the equivalent resistance R32, can be sufficiently reduced.
FIG. 2A shows a schematic plan view of another twin-well semiconductor device for an analog/digital hybrid circuit disclosed in Japanese Patent Laid-Open Publication No. 1(1989)-112765. FIG. 2B is a sectional view taken along dashed line B-B' of FIG. 2A. In the vicinity of a main surface of a P-substrate 30 having a first impurity concentration, P-wells 33 and N-wells 32 each having an impurity concentration higher than the first impurity concentration are formed on an undoped region of the P-substrate 30 in a twin well fashion. Further, there are formed circuit blocks CB31 and CB32 each having a circuit area spreading over both one of the N-wells 32 and the P-well 33.
A cross-talk reducing N-well 32' having a predetermined width is formed between the P-wells 33 to surround the periphery of circuit block CB31, and the N-well 32' is electrically connected to a Vdd source line (high potential source line) 38 through contact holes 35 formed in an insulator layer 37. With this arrangement, since the semiconductor device shown in FIGS. 2A and 2B is provided with the cross-talk reducing N-well 32' which is formed between circuit block CB32 and circuit block CB31 and which is connected to the Vdd source line 38, the DC component of noise flowing through the surface of the P-substrate 30 including the P-well 33 can be reduced.
With the semiconductor device shown in FIGS. 2A and 2B, circuit block CB32 and circuit block CB31 are electrically coupled with each other through a parallel circuit, which is composed of a serial impedance including the equivalent resistances R33 and R35 of the P-wells 33, the equivalent resistance R34 of the cross-talk reducing N-well 32' and the junction capacitances C31 and C32 formed between the P-wells 33 and the N-well 32', and the equivalent resistance R32 of the undoped region 31 of the P- substrate 30 located below the wells 33 and 32'. The resistivity r.sub.NWEL of the cross-talk reducing N-well 32' (including an impurity at ND=1E17 cm-3, for example) is very low, i.e., about 0.1 .OMEGA.-cm, so that the equivalent resistance R34 of the N-well 32' is very low, comparable to the equivalent resistances R33 and R35 of the P-wells 33. The junction capacitance per unit area C between the P-wells 33 and the N-well 32' is expressed by the following formulas: EQU C=.sqroot. {(q.multidot.X.sub.Si .multidot.e.sub.o .multidot.NA.multidot.ND)/(2(NA+ND).multidot.(.phi.+.vertline.VR.vertline. ))} (1-a) EQU .phi.=(kT/q).multidot.ln{(NA.multidot.ND)/n.sub.i.sup.2 } (1-b)
wherein q is the charge of an electron, X.sub.Si is the relative permittivity of silicon, e.sub.o is the permittivity in a vacuum, k is Boltzmann's constant, and n.sub.i is the concentration of electrons in an intrinsic silicon semiconductor.
Assuming that the bias voltage VR is -5 V, the junction capacitance per unit area C becomes C=2.6E-08 F/cm.sup.2, which is considerably large value. Therefore, the junction capacitances between the P-wells 33 and the N-well 32' are considerably large, and the impedance of the serial circuit including R33, R34, R35, C31 and C32 therefore becomes low, especially in a high-frequency range.
Noise generated by circuit block CB32 forming a digital circuit block includes many high-frequency components as well as a DC component. Since circuit block CB32 and circuit block CB31 shown in FIGS. 2A and 2B are coupled through the serial circuit including R33, R34, R35, C31 and C32 and having an impedance especially low in a high-frequency range, as described above, the reduction of noise by the serial circuit is not sufficient for the high-frequency components of the noise.
Accordingly, in both the conventional twin-well semiconductor devices as described above, noise propagating between circuit blocks cannot be sufficiently reduced. This means that an analog signal generated in an analog/digital circuit includes a considerably large noise, resulting in an insufficient accuracy of the analog signal due to a low S/N ratio in the analog signal.